VR Applications and block diagrams

VR: Interface Block Diagram
VR: Multiprocessor idea

I see I forgot to add some of the comments to the second schematics.

The right-most chips are supposed to be RAM/EEPROM (general Memory) chips, and my original idea on how to prevent data collision in accessing the middle (public) block is to have the CPU and DSP chips clocked 180 degrees out of phase from one another. Both the CPU and DSP chips have 32 bit wide address and data lines. In my diagram, and my initial concept, I evenly split ALL the address lines; this was not necessary. Each processor need only reserve two address lines to specify Public or Private memory.

The idea behind this is that a processor can write to both memory types (public and private as I have called them) simultaneously. Again, to reduce number of required commands, hopefully increasing overall efficiency and portability of this design, the CPU addresses interface devices as though it were memory.

As you may well realize, this leaves two unused address lines per memory block; some variations on making use of this "extra" memory are as follows:

There are two processor chips, and three memory blocks - these two surplus data lines can be handled with some simple logic to enable both processors to write to Public (1,1), VDSP Private (0,1), CPU Private (1,0), or dual write to Public and processor-specific Private memory pseudo-(0,0) on their respective clock cycles. Unfortunately this also leaves the true (0,0) condition of those address lines unused. One possible application is to triple-phase the clock cycle (120 degrees) and on the extra phase, provide access to this extra block to peripherals, a memory-management CPU/watchdog...
Using the tri-phasing mentioned above, the extra address lines could be used for an effectively indepedant CPU, more along the lines of a "standard" computer (PC, MAC, AMIGA). This system would turn into a triple processor system: The VROS CPU/VDSP combo, and a second "standard" PC unit with only 30 address lines able to address memory. The remaining 2 address lines could be used for addressing other peripherals on that sub-unit. In a sense, this would be a VR-enhanced PC. Traditional PC applications would run on the standard sub-unit, in a full VROS environment. This could be an interesting little hybrid system...

Hope this clears up any confusion generated in any of my discussions elsewere, i.e. the VRML list